Journal of System-on-Chip (JSoC)

ISSN: 1552-4809

  (for discussion)


Driven by the rapid growth of the Internet, communication technologies, pervasive computing, automobiles, airplanes, wireless and portable consumer electronics, Systems-on-Chip (SoC) has moved from craft to an emerging and very promising discipline in today's electronic industry. SoCs have created new challenges in Design Methods, Design Tools, Design Automation, Manufacturing, Technology, and Test.

JSoC addresses the most innovative SoC developments and the latest advances in VLSI/ULSI/GSI technology and design capabilities, and their application to meeting the future challenges.


The objective of the SoC journal is to provide an outstanding channel for academics, industrial professionals, educators and policy makers working in the field to contribute and to disseminate innovative and important  new work in System-on-Chip.


Scientists, engineers, researchers, educators, managers, and industrial professionals.


JSoC is a peer-reviewed international journal, initially published quarterly, providing an international forum to report, discuss and exchange experimental or theoretical results, novel designs, work-in-progress, experience, case studies, and trend-setting ideas. Papers should be of a quality that represents the state-of-art and the latest advances in System-on-Chip in terms of time-to-market, cost, code size, weight, testability, power, real-time behavior, and stimulating future trends.

Subject Coverage:

The SoC journal covers all aspects of the System-on-Chip. Topics of interest include, but are not limited to:

1. Enabling Technologies for SoC
        Embedded DRAMs/Flash Memories
        Deep Sub-micron Technologies
        Optical Interconnects

2. SoC Specific Design Methodologies
        Reusable and Embedded Cores/Macros, Memories
        Technology Independent Methodologies
        On-Chip Communication and Interconnects for SoC
        Smart Sensors Integration
        Design of Reconfigurable SoCs
        Library Development
        SoC/IP Validation

3. Common Design Methodologies
        High Performance, Low Power Design
        Analog & Mixed-Signal Design
        Timing Methodologies, Sync/Async Design, Clocking
        Reconfigurable/Scalable Design

4. Design Automation
        System Interconnects, Interconnect Modeling, Signal Integrity
        Hardware/Software Co-Design, Verification
        High Level Design and Synthesis
        Logic Design and Synthesis
        Physical Design and Synthesis, IP Issues and Reuse
        SoC Specific CAD Tools

5. Test and Verification
        Formal Verification
        Simulation and Modeling
        Design for Testability
        Test Synthesis
        Built-In Self-Test
        Fault Modeling, IDDQ
        Failure Analysis

6. SoC Manufacturing
        Signal Integrity and EMI
        Packaging and I/O Interfacing
        SoC Testing, Power Measurement, Burn-In
        SoC Fabrication Technologies

7. Common SoC Issues
        Project Management, Distributed Development Teams
        Intellectual Property, Patent and Legal Issues
        SoC Success Stories, Case Studies
        Future SoC Trends and Limits
        SoC Overview and Tutorial Papers

8. SoC Applications
        Communication, Networking, Internet, e-Business
        Signal/Image Processing, Multimedia
        Portable and Wireless Systems
        Wireless/Pervasive Computing
        Consumer and Defense Electronics
        FPGAs and Reconfigurable SoCs
        Embedded and Real-time Systems
        Other SoC Applications

The Editorial Board:

Professor Laurence T. Yang, St. Francis Xavier Univ, Canada

Regional Editors-in-chief:
Dr Yervant Zorian, Virage Logic, USA (North & South America)
Dr Hiroto Yasuura, Kyushu University, Japan (Asia, Pacific Areas)
Dr Ahmed Amine Jerraya, TIMA/INPG, France (Europe, Africa)

Associate editors:
to be selected


Rinton Press, New Jersey, USA


1552-4809 (print) and 1552-4817 (online)